Organization & Role

Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne’s products in many ways must be ahead of the semiconductor industry for our customers to ship production chips/products.

You will join a best-in-class Digital team as an “ASIC Digital Design Engineer” working in collaboration with an Analog team and product architects to develop Teradyne’s next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bringup.

In this role you will be responsible for:

• 
  Writing specifications for digital blocks in close collaboration with chip architects
• Coding RTL for digital blocks in Verilog
• Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success
• Writing timing constraints for logic synthesis and Physical Design
• Running Logical Equivalency and Static Timing Analysis
• Working closely with Physical Design engineers performing layout to optimize the design
• Participating in detailed reviews for ASIC Tapeout
• Provide support for bringup and debug of the silicon in the lab

Basic Qualifications & Skills

Key Qualifications (college level experience)

• 
  Logic design and RTL coding with Verilog
• Design of state machines, FIFOs, data paths, arbiters, memory interfaces and math functions
• Verification methodologies and simulation and debug of RTL Designs
• Experience with automation through scripting such as Perl, Python, Tcl & Make
• Any experience with industry standards: PCIe, DDR Memory, High Speed Serdes a plus
• Hardware performance modeling in C++ a plus
• Candidate must be available to be on-site in North Reading, MA.

Education

BS or MS in Electrical Engineering or PhD